The increasing speed with which multiple types of data, such as text, audio and video, are transported over existing communication networks has brought to the fore the reliability with which such data transportation is carried out. In accordance with one conventional method, to ensure reliable data transfer, the data is first encoded with a reference clock signal at the transmitting end of the network to generate a composite signal. Thereafter, the composite signal is transmitted over the network to the receiving end. At the receiving end, the data and clock signals are recovered from the composite signal to ensure that the data and clock signals remain synchronous with respect to each other.
The clock and data recovery (CDR) is typically carried out, for example, by a phase locked loop (PLL). In operation, a phase locked loop maintains a fixed relationship between the phase and frequency of the signal it receives and those of the signal it generates. A phase-locked loop often includes a phase detector (PD) that receives a pair of signals, and in response, generates a pair of output signals representative of the difference between the phases of the two received signals.
One widely known phase detector, referred to as Hogge phase detector, and which can only rely on the non-return to zero (NRZ) or pulse width modulation (PWM) property of data to re-time the input data at the optimal sampling point is shown in FIG. 1. Phase detector (PD) 50 requires that the duty cycle distortion of the recovered clock be kept at minimum. The operation of PD 50 is described further below.
A timing diagram with the clock aligned nearly perfectly aligned to the input data transitions is shown in FIG. 2 for a NRZ or PWM data stream. The input NRZ data stream signal is provided to PD 50 on data signal line labeled Rdata, which is applied to the input terminal D of flip-flop 12. The output QN1 of flip-flop 12 is supplied to the input terminal D of flip-flop 14.
Clock signal Rclk is applied to the input clock terminal CP of flip-flop 12, and the inverse of clock signal Rclk is applied to the input clock terminal of flip-flop 14. The input and output of the flip-flop 12 are provided to an exclusive-OR gate 24 to provide signal P_UP signal. The input and output of the flip-flop 14 are provided to a second exclusive-OR gate 26, to provide signal P_DN. Signals P_UP and P_DN are provided to a charge pump (not shown).
As can be seen from the block diagram of FIG. 1 and the timing diagram of FIG. 2, the P_UP pulses are generated during the time interval between data transitions and the next rising edge of the clock. Every P_UP pulse generates a P_DN pulse with a fixed width of half of the clock period. Ideally the width of the P_UP and P_DN pulses should be equal to half of the clock period. When the clock leads or lags from this ideal position, the P_UP pulse becomes smaller or larger than the P_DN pulse, respectively. The P_UP and P_DN pulses are fed to the charge pump and loop-filter which are part of a phase-locked loop (PLL) (not shown). The difference between the pulse width of the signals P_UP and P_DN is processed and delivered as a feedback signal to control the frequency of the oscillator in the PLL
When the clock is aligned nearly perfectly to the input data transitions, the difference between the pulse widths of P_UP and P_DN is equal to nearly zero, and the PLL is in a phase-locked condition. It is seen that the sampling point of the data is optimal since the sampling (rising) edge of the clock is located near the center of the data windows, thus providing the maximum noise margin. Referring to FIG. 2, it is seen that each NRZ of data RDATA pulse provides two P_UP signals and two P_DN signals, resulting in two ramp-up and ramp-down transitions of the loop filter voltage, as shown at the bottom of FIG. 2.
FIG. 3 illustrates what happens if RZ or PPM type data (the pulse width of the signal could be much smaller or much bigger than one period of the clock) is used for the input RDATA signal shown at the top of FIG. 3. As can be seen, since the clock rising edge 32 is aligned with the falling edge 34 of the RZ data, a misalignment may result in the one pulse not being sampled. Accordingly, PD 50 is very susceptible to noise for RZ data and is also not suitable for RZ or Pulse Position Modulation (PPM) data format used in the magnetic recording technology or the communication technology.
FIG. 4 is a simplified block diagram of a tri-wave phase detector 100, as known in the prior art. Tri-wave phase detector 100 is shown as including three flip-flops and three XOR gates. Tri-wave detector 100 provides a reduced sensitivity to data transition density. However, tri-wave detector 100 is more sensitive to duty cycle distortion in the clock signal than is Hogge's phase detector and it is also more complex than Hogge's PD.
FIG. 5 is a simplified block diagram of a modified tri-wave phase detector 150, as known in the prior art. Modified tri-wave phase detector 150 uses two distinct down-integration intervals clocked on opposite edges of the clock, rather than a single down-integration of twice the strength clocked on a single edge. This enables tri-wave phase detector 150 to have a relatively improved duty cycle performance compared to tri-wave phase detector 100. However, phase detectors that are based on Hogge (both tri-wave phase detector 100 as well as modified tri-wave phase detector 150) do not function properly with RZ data stream. Moreover, the center offsets of both these detectors are dependent on the duty cycle of the clock signal CLK.
U.S. Pat. No. 6,324,236 also describe examples of different circuits adapted to detect the phase of a RZ data signal. However, the circuits disclosed in this patent utilize the pulse width of the clock and hence their performance suffers from the clock duty cycle distortion. Moreover, they cannot function properly if the pulse width of the RDATA is greater than one period of the clock.